1. Field of the Invention
The invention generally relates to a bus architecture for a computer system; and in particular, the present invention relates to a bus architecture which enhances the testability of an integrated computer system.
2. Background of the Invention
In a computer system in which a combination of modules are coupled to each other over a bus, a bus architecture defines the framework for communication among the modules.
In a computer system where the modules are not integrated, such as a PC board in which a number of integrated circuit (IC) devices implements the modules, each module of the system can usually be tested individually. However, when these modules, or functional elements, are integrated onto a single IC device, the input and output nodes of an individual module within the IC device are no longer directly accessible, since the input and output nodes of an individual module have become internal nodes of the IC device. In an integrated circuit, the modules are tested by applying and reading signals at the external input and output pins of the integrated circuit. Debugging of the IC device is particularly difficult when the internal nodes of the device are not directly accessible.
When analog circuitry is integrated with digital circuitry on a single IC device, testing is even more difficult as there is often a need to test the analog circuitry apart from the digital circuitry, and vice versa. It is often desirable to test analog circuits using analog signals and digital circuits using digital signals. But separate testing of the digital and analog portions of an integrated analog-digital device is difficult because the connections between the analog and digital circuits are internal nodes which are not accessible directly from the external device pins. For example, in a signal processing device, an analog-to-digital converter (ADC) is coupled to a digital signal processor (DSP). In such a signal processing device, the ADC provides from analog signals digitized data for the DSP to perform filtering and conditioning functions. Typically, the digitized data generated from the ADC are coupled to the DSP on internal nodes and are not available to external device pins. Thus, when the signal processing device fails, it may be difficult to ascertain the cause of the failure.
Therefore, in an integrated computer system, there is a need to enhance testability by providing access to the internals nodes of the modules within the integrated system. Because these nodes are generally numerous and device pins are scarce, it is not feasible to merely provide these internal nodes directly to external device pins. Thus, it would be desirable to provide a bus architecture which allows access to internal nodes of an integrated device without requiring a substantial number of additional external device pins.
Further, in designing a bus architecture for an integrated modular system, it is desirable to provide a bus architecture design which has a high degree of portability. When a bus architecture can be readily adapted for use in other computer systems, significant cost saving in design and development of subsequent products can be achieved.
In an IC device, the modules within the device may be synchronized to different clock frequencies. When data signals cross between different clock domains, the data signals have to be resynchronized to the new clock domain. Prior art approaches to resynchronizing signals crossing between different clock domains are not satisfactory. One problem with prior art resynchronizing method is that it is difficult to predict which clock cycle the final synchronized signal will appear. Even though data accuracy is preserved, the final synchronized signal may appear unpredictably at one of several clock cycles because of jittering between related clock edges. This makes automatic testing of the IC device impossible because the output data is not available at a consistent clock cycle to allow the tester to retrieve the data for comparison. Another problem with the prior art approach is that data coherency across a parallel data bus is not maintained. Because the resynchronized signal of each bit line of the parallel bus may not all appear within the same clock cycle, the resynchronized signal across the bus is corrupted after crossing the clock boundary. Therefore, an improved synchronized technique which can guarantee signal coherency and predictability for signals crossing over different clock domains is desired.